CoreForth-0

cortex/boards/nucleo-l053r8.ft.md

Host ———————————————————————

::host::

::dtc:: cr ." *** DTC not supported ***" cr bye

../janus/compiler.ft

Target ——————————————————————-

::target::

$08000000 to trom
$20000000 to tram
        4 to tcell

trom tdp !
tram tvp !

tram $00001000 + t, 0 t,
trom $00000400 + torg

../cpus/cortex-m0/armv6-m-primitives.ft

::stc:: include ../cpus/cortex-m0/threading-stc.ft
::itc:: include ../cpus/cortex-m0/threading-itc.ft

          $FC buffer: psp
             variable s0
          $FC buffer: rsp
             variable r0

../common/core.ft

../../common/core.ft

../dictionary/common.ft

../cpus/stm32l0xx/rcc.ft

../cpus/stm32l0xx/flash.ft

../cpus/stm32l0xx/gpio.ft

../cpus/stm32l0xx/usart.ft

../cpus/stm32l0xx/spi.ft

: emit          begin USART2_ISR c@ %10000000 and until USART2_TDR c! ;
: key?          USART2_ISR c@ %00100000 and ;
: key           begin key? until USART2_RDR c@ ;

../../common/output.ft

../../common/input.ft

../dictionary/full.ft

::stc:: include ../common/threading-stc.ft
::itc:: include ../common/threading-itc.ft

../../common/exception.ft

../../common/control-flow.ft

../common/compiler.ft

../../common/interpret.ft

../../common/utils.ft

../janus/init.ft

Switch to MSI16 as system clock source

: 16mhz        %00000001 RCC_CR ! begin RCC_CR @ %00000100 and until
               %00000001 RCC_CFGR !
               ;

Enable USART2 with 115200bps, using MSI16 as clock source and PA2 and PA15 as TX/RX pins

: uart-init    %100000000000000000 RCC_APB1ENR bis!
               GPIOA_MODER dup @ $FFFFFF0F and $000000A0 or swap !
               GPIOA_AFRL dup @ $FFFF00FF and $00004400 or swap !
               RCC_CCIPR dup @ $FFFFFFF3 and $00000008 or swap !
               #138 USART2_BRR !
               %00001101 USART2_CR1 bis!
               ;

Enable LED at PA5 (overlaps with SPI2 SCK)

: led-init     GPIOA_MODER dup @ $FFFFF3FF and $00000400 or swap ! ;
: +led         $00000020 GPIOA_BSRR ! ;
: -led         $00000020 GPIOA_BRR ! ;
: ~led         GPIOA_IDR @ $00000020 xor GPIOA_ODR ! ;

Enable button at PC13

: button-init  GPIOC_MODER dup @ $F3FFFFFF and swap ! ;
: button?      GPIOC_IDR @ $2000 and 0= ;

Enable SPI1 with system clock divided by two as clock and PB6 as SS pin

: spi-init     %1000000000000 RCC_APB2ENR bis!
               GPIOB_MODER dup @ $FFFFCFFF and $00001000 or swap !
               $40 GPIOB_BSRR !
               GPIOA_MODER dup @ $FFFF03FF and $0000A800 or swap !
               GPIOA_OSPEEDR dup @ $FFFF03FF and $0000A800 or swap !
               GPIOA_AFRL dup @ $000FFFFF and swap !
               0 SPI1_CR1 !
               %1100000100 SPI1_CR1 2dup !
               swap %01000000 or swap !
               ;

: +spi         $40 GPIOB_BRR ! ;
: -spi         $40 GPIOB_BSRR ! ;
: >spi>        begin SPI1_SR @ %10 and until
               SPI1_DR c!
               begin SPI1_SR @ %1 and until
               SPI1_DR c@
               ;
: >spi         >spi> drop ;
: spi>         $ff >spi> ;

NRF24 CE pin

: rf-ce-init   GPIOC_MODER dup @ $03FFFFFF and $10000000 or swap ! ;
: -rf-ce       $8000 GPIOC_BRR ! ;
: +rf-ce       $8000 GPIOC_BSRR ! ;

: hw-init      %00000000000000000111 RCC_IOPENR bis!
               16mhz
               led-init
               button-init
               uart-init
               spi-init
               ;

Include any extra files:

include-extras

: cold         s0 sp! r0 rp!
               0 (source-id) !
               setup-vars
               hw-init
               hex
               abort
               begin wfi again
               ;

Host ———————————————————————

::host::

../janus/save-image.ft

::stc:: s" nucleo-l053r8-stc.hex" save-hex
::itc:: s" nucleo-l053r8-itc.hex" save-hex